The present invention relates generally to computer memory, and more specifically to a hybrid storage system that employs reconfigurable memory.
Flash memories are increasingly being used as non-volatile storage media in both consumer and enterprise applications. Flash memory stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Other flash memory devices, such as multi-level cell (MLC) devices, including triple-level cell (TLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells. One limitation of flash memory is that, although it can be read or programmed a byte or a word at a time in a random access fashion, it can only be erased one block at a time. Flash memory is also characterized by a limited endurance (also referred to as a “limited life”) due to its ability to undergo only a finite number of program-erase cycles. For example, some commercially available flash products are guaranteed to withstand around one-hundred thousand program-erase cycles before the wear begins to deteriorate the integrity of the storage. Various techniques (e.g., wear leveling, data coding) have been developed to increase the overall endurance of a flash device, however, these techniques often result in impacting other memory metrics such as capacity, read performance, write performance, and power usage.